= RISC-V

x0      zero    X
x1      ra      R  return address
x2      sp      E  stack pointer
x3      gp      X  global pointer
x4      tp      X  thread pointer
x5      t0      R  temporary/alternate link register
x6–7    t1–2    R  temporaries
x8      s0/fp   E  saved register/frame pointer
x9      s1      E  saved register
x10–11  a0–1    R  function arguments / return value
x12–17  a2–7    R  function arguments
x18–27  s2–11   E  saved registers
x28–31  t3–6    R  temporaries
f0–7    ft0–7   R  FP temporaries
f8–9    fs0–1   E  FP saved registers
f10–11  fa0–1   R  FP arguments/return values
f12–17  fa2–7   R  FP arguments
f18–27  fs2–11  E  FP saved registers
f28–31  ft8–11  R  FP temporaries
––––––––––––––––––––––––––––––––––––––––––
register        X=none R=caller-saved E=callee-saved
        API name   Description

RV32E: only x0–x15
f-register only with F-Extension




{RV32I, RV32E, RV64I, RV128I}

Extensions:
  Zifencei → Fence Instruction
  M → Integer Multiplication and Division
  A → Atomic Instructions
  Zicsr → Control and Status Register
  F → Single-Precision Floating-Point
  D → Double-Precision Floating-Point
  Q → Quad-Precision Floating-Point
  RVWMO → RISC—V Weak Memory Ordering
  L → Decimal Floating-Point
  C → Compressed Instructions
  B → Bit Manipulation
  J → Dynamically Translated Languages
  T → Transactional Memory
  P → Packed-SIMD Instructions
  V → Vector Operations
  Zam → Misaligned Atomics
  Ztso → Total Store Ordering

General-purpose ISA = (RV32I or RV64I) + I M A F D extensions + Zicsr + Zifencei = IMAFDZicsr_Zifencei = “G”